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filterless high efficiency mono 2.8 w class-d audio amplifier ssm2305 rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2008 analog devices, inc. all rights reserved. features filterless class-d amplifier with - modulation no sync necessary when using multiple class-d amplifiers from analog devices, inc. 2.8 w into 4 load and 1.6 w into 8 load at 5.0 v supply with <10% total harmonic distortion (thd) 89% efficiency at 5.0 v, 1.3 w into 8 speaker >98 db signal-to-noise ratio (snr) single-supply operation from 2.5 v to 5.5 v 20 na ultralow sh utdown current short-circuit and thermal protection available in 8-lead, 3 mm 3 mm lfcsp and msop pop-and-click suppression built-in resistors reduce board component count fixed and user-adjustable gain configurations applications mobile phones mp3 players portable gaming portable electronics educational toys general description the ssm2305 is a fully integrated, high efficiency, class-d audio amplifier designed to maximize performance for mobile phone applications. the application circuit requires a minimum of external components and operates from a single 2.5 v to 5.5 v supply. it is capable of delivering 2.2 w of continuous output power with less than 1% thd + n driving a 4 load from a 5.0 v supply. it has built-in thermal shutdown and output short- circuit protection. the ssm2305 features a high efficiency, low noise modulation scheme that does not require external lc output filters. the modu- lation provides high efficiency even at low output power. the ssm2305 operates with 90% efficiency at 1.3 w into 8 or 83% efficiency at 2.2 w into 4 from a 5.0 v supply and has an snr of >98 db. spread-spectrum pulse density modulation is used to provide lower emi-radiated emissions compared with other class-d architectures. the ssm2305 has a micropower shutdown mode with a maximum shutdown current of 30 na. shutdown is enabled by applying a logic 0 to the sd pin. the device also includes pop-and-click suppression circuitry. this minimizes voltage glitches at the output during turn-on and turn-off, thus reducing audible noise on activation and deactivation. the fully differential input of the ssm2305 provides excellent rejection of common-mode noise on the input. input coupling capacitors can be omitted if the dc input common-mode voltage is approximately v dd /2. the ssm2305 has excellent rejection of power supply noise, including noise caused by gsm transmission bursts and rf rectification. psrr is typically 60 db at 217 hz. the default gain of the ssm2305 is 18 db, but users can reduce the gain by using a pair of external resistors. the ssm2305 is specified over th e commercial temperature range (?40 c to +85 c). it is available in both an 8-lead, 3 mm 3 mm lead frame chip scale package (lfcsp) and an 8-lead mini small outline package (msop). functional block diagram 07243-001 shutdown 0.1f vdd pop/click suppression out+ out? in+ vbatt 2.5v to 5.5v in? modulator ( - ) gnd 10f 47nf* * input capacitors are optional if input dc common-mode voltage is approximately v dd /2. 47nf* sd audio in? audio in+ ssm2305 37k ? 296k? 296k? 37k ? fet driver bias internal oscillator figure 1.
ssm2305 rev. a | page 2 of 16 table of contents features .............................................................................................. 1 ? applications ....................................................................................... 1 ? general description ......................................................................... 1 ? functional block diagram .............................................................. 1 ? revision history ............................................................................... 2 ? specifications ..................................................................................... 3 ? absolute maximum ratings ............................................................ 4 ? thermal resistance ...................................................................... 4 ? esd caution .................................................................................. 4 ? pin configurations and function descriptions ........................... 5 ? typical performance characteristics ............................................. 6 ? applications information .............................................................. 11 ? overview ..................................................................................... 11 ? gain .............................................................................................. 12 ? pop-and-click suppression ...................................................... 12 ? output modulation description .............................................. 12 ? layout .......................................................................................... 12 ? input capacitor selection .......................................................... 12 ? proper power supply decoupling ............................................ 13 ? outline dimensions ....................................................................... 14 ? ordering guide .......................................................................... 14 ? revision history 7/08rev. 0 to rev. a changes to figure 1 .......................................................................... 1 change to shutdown current parameter, table 1 ........................ 3 change to differential input impedance parameter, table 1 ..... 3 added exposed pad notation to figure 2 ..................................... 5 change to figure 24 ......................................................................... 9 changes to figure 32 and figure 33 ............................................. 11 changes to gain section ................................................................ 12 updated outline dimensions ....................................................... 14 3/08revision 0: initial version
ssm2305 rev. a | page 3 of 16 specifications v dd = 5.0 v, t a = 25 o c, r l = 8 + 33 h, unless otherwise noted. table 1. parameter symbol conditions min typ max unit device characteristics output power p o r l = 8 , thd = 1%, f = 1 khz, bw = 20 khz 1.34 w r l = 8 , thd = 1%, f = 1 khz, bw = 20 khz, v dd = 3.6 v 0.68 w r l = 8 , thd = 10%, f = 1 khz, bw = 20 khz 1.67 w r l = 8 , thd = 10%, f = 1 khz, bw = 20 khz, v dd = 3.6 v 0.85 w r l = 4 , thd = 1%, f = 1 khz, bw = 20 khz 2.22 w r l = 4 , thd = 1%, f = 1 khz, bw = 20 khz, v dd = 3.6 v 1.1 w r l = 4 , thd = 10%, f = 1 khz, bw = 20 khz 2.8 w r l = 4 , thd = 10%, f = 1 khz, bw = 20 khz, v dd = 3.6 v 1.3 w efficiency p o = 1.3 w, 8 89 % total harmonic distortion + noise thd + n p o = 1 w into 8 , f = 1 khz 0.02 % p o = 0.5 w into 8 , f = 1 khz, v dd = 3.6 v 0.02 % input common-mode voltage range v cm 1.0 v dd ? 1 v common-mode rejection ratio cmrr gsm v cm = 2.5 v 100 mv at 217 hz, output referred 55 db average switching frequency f sw 280 khz differential output offset voltage v oos g = 18 db 2.0 mv power supply supply voltage range v dd guaranteed from psrr test 2.5 5.5 v power supply rejection ratio psrr v dd = 2.5 v to 5.0 v, dc input floating 70 85 db psrr gsm v ripple = 100 mv at 217 hz, inputs ac gnd, c in = 0.1 f 60 db supply current i sy v in = 0 v, no load 3.2 ma v in = 0 v, 3.3 ma v in = 0 v, no load, v dd = 3.6 v 2.8 ma v in = 0 v, v dd = 3.6 v 2.9 ma v in = 0 v, no load, v dd = 2.5 v 2.4 ma v in = 0 v, v dd = 2.5 v 2.4 ma shutdown current i sd sd = gnd 20 30 na gain control closed-loop gain av 18 db differential input impedance z in sd = v dd 37 k shutdown control input voltage high v ih i sy 1 ma 1.2 v input voltage low v il i sy 300 na 0.5 v wake-up time t wu sd rising edge from gnd to v dd 30 ms shutdown time t sd sd falling edge from v dd to gnd 5 s output impedance z out sd = gnd >100 k noise performance output voltage noise e n v dd = 3.6 v, f = 20 hz to 20 khz, inputs are ac grounded, a v = 18 db, a-weighted 40 v signal-to-noise ratio snr p o = 1.4 w, r l = 8 98 db
ssm2305 rev. a | page 4 of 16 absolute maximum ratings absolute maximum ratings apply at t a = 25c, unless other- wise noted. table 2. parameter rating supply voltage 6 v input voltage v dd common-mode input voltage v dd storage temperature range ?65c to +150c operating temperature range ?40c to +85c junction temperature range ?65c to +165c lead temperature (soldering, 60 sec) 300c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal resistance ja is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. table 3. package type ja jc unit 8-lead, 3 mm 3 mm lfcsp 62 20.8 c/w 8-lead msop 210 45 c/w esd caution
ssm2305 rev. a | page 5 of 16 pin configurations and function descriptions pin 1 indicator notes: 1. nc = no connect. 2. exposed pad is not connected internally. for increased reliability of the solder joints and maximum thermal capability it is recommended that the pad be soldered to the ground plane. top view (not to scale) ssm2305 sd 1 2 nc 3 in+ 4 in? 7gnd 8out? 6vdd 5out+ 07243-002 figure 2. lfscp pin configuration sd 1 nc 2 in + 3 in? 4 out? 8 gnd 7 vdd 6 out+ 5 ssm2305 top view (not to scale) 07243-103 nc = no connect figure 3. msop pin configuration table 4. pin function descriptions pin no. mnemonic description 1 sd shutdown input. active low digital input. 2 nc no connect. this pin has no function; tie it to gnd. 3 in+ noninverting input. 4 in? inverting input. 5 out+ noninverting output. 6 vdd power supply. 7 gnd ground. 8 out? inverting output.
ssm2305 rev. a | page 6 of 1 6 typical performance characteristics 100 10 1 0.1 0.01 0.0001 10 0.001 thd + n (%) 0.01 0.1 1 output power (w) 07243-004 v dd = 2.5v v dd = 5v v dd = 3.6v r l = 4 ? + 33h gain = 18db figure 4. thd + n vs. output power into 4 + 33 h, a v = 18 db 100 10 1 0.1 0.01 0.001 0.0001 10 0.001 0.01 0.1 1 output power (w) 07243-005 v dd = 2.5v r l = 4 ? + 33h gain = 6db v dd = 5v v dd = 3.6v thd + n (%) figure 5. thd + n vs. output power into 4 + 33 h, a v = 6 db 100 10 1 0.1 0.01 0.001 0.0001 10 0.001 0.01 0.1 1 output power (w) 07243-006 r l = 8 ? + 33h gain = 18db thd + n (%) v dd = 2.5v v dd = 5v v dd = 3.6v figure 6. thd + n vs. output power into 8 + 33 h, a v = 18 db 100 10 1 0.1 0.01 0.001 0.0001 10 0.001 0.01 0.1 1 output power (w) 07243-007 v dd = 2.5v r l = 8 ? + 33h gain = 6db v dd = 5v thd + n (%) v dd = 3.6v figure 7. thd + n vs. output power into 8 + 33 h, a v = 6 db 100 10 1 0.1 0.01 0.001 10 100 thd + n (%) 1000 100000 10000 07243-008 0.5w 2w v dd = 5v gain = 18db r l = 4 ? + 33h 1w frequency (hz) figure 8. thd + n vs. frequency, v dd = 5 v, r l = 4 + 33 h, a v = 18 db 100 10 1 0.1 0.01 0.001 100 10 1 0.1 0.01 0.001 10 100 thd + n (%) 1000 100000 10000 frequency (hz) 07243-009 0.25w 0.5w v dd = 5v gain = 18db r l = 8 ? + 33h 1w figure 9. thd + n vs. frequency, v dd = 5 v, r l = 8 + 33 h, a v = 18 db
ssm2305 rev. a | page 7 of 16 100 10 1 0.1 0.01 0.001 10 100 thd + n (%) 1000 100000 10000 07243-010 1w v dd = 3.6v gain = 18db r l = 4 ? + 33h 0.5w frequency (hz) 0.25w figure 10. thd + n vs. frequency, v dd = 3.6 v, r l = 4 + 33 h, a v = 18 db 100 10 1 0.1 0.01 0.001 10 100 thd + n (%) 1000 100000 10000 07243-011 v dd = 3.6v gain = 18db r l = 8 ? + 33h 0.5w 0.25w 0.25w frequency (hz) figure 11. thd + n vs. frequency, v dd = 3.6 v, r l = 8 + 33 h, a v = 18 db 100 10 1 0.1 0.01 0.001 10 100 thd + n (%) 1000 100000 10000 07243-012 v dd = 2.5v gain = 18db r l = 4 ? + 33h 0.5w 0.25w 0.125w frequency (hz) figure 12. thd + n vs. frequency, v dd = 2.5 v, r l = 4 + 33 h, a v = 18 db 100 10 1 0.1 0.01 0.001 10 100 thd + n (%) 1000 100000 10000 07243-013 v dd = 2.5v gain = 18db r l = 8 ? + 33h 0.25w 0.075w 0.125w frequency (hz) figure 13. thd + n vs. frequency, v dd = 2.5 v, r l = 8 + 33 h, a v = 18 db 3.8 3.6 3.4 3.2 3.0 2.8 2.6 2.4 2.2 2.0 2.53.03.54.04.55.05.56. 07243-014 supply current (ma) supply voltage (v) 0 r l = 8 ? + 33h r l = 4 ? + 33h no load figure 14. supply current vs. supply voltage 12 10 8 6 4 2 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 07243-015 shutdown current (a) shutdown voltage (v) v dd = 5v v dd = 2.5v v dd = 3.6v figure 15. shutdown current vs. shutdown voltage
ssm2305 rev. a | page 8 of 16 .0 3.0 2.5 2.0 1.5 1.0 0.5 0 2.5 3.0 10% 1% 3.54.04.55 07243-016 output power (w) supply voltage (v) f = 1khz gain = 18db r l = 4 ? + 33h figure 16. maximum output power vs. supply voltage, r l = 4 + 33 h, a v = 18 db 3.0 2.5 2.0 1.5 1.0 0.5 0 2.5 3.0 3.5 10% 1% 4.0 4.5 5.0 07243-017 output power (w) supply voltage (v) f = 1khz gain = 6db r l = 4 ? + 33h figure 17. maximum output power vs. supply voltage, r l = 4 + 33 h, a v = 6 db 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 2.5 3.0 3.5 10% 1% 4.0 4.5 5.0 07243-018 output power (w) supply voltage (v) f = 1khz gain = 18db r l = 8 ? + 33h figure 18. maximum output power vs. supply voltage, r l = 8 + 33 h, a v = 18 db 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 2.5 3.0 3.5 10% 1% 4.0 4.5 5.0 07243-019 output power (w) supply voltage (v) f = 1khz gain = 6db r l = 8 ? + 33h figure 19. maximum output power vs. supply voltage, r l = 8 + 33 h, a v = 6 db 100 90 80 70 60 50 40 30 20 10 0 0 0.20.40.60.81.01.21.41.61.82.0 07243-020 efficiency (%) output power (w) v dd = 2.5v r l = 4 ? + 33h gain = 18db v dd = 5v v dd = 3.6v figure 20. efficiency vs. output power into 4 + 33 h 100 90 80 70 60 50 40 30 20 10 0 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 07243-021 efficiency (%) output power (w) v dd = 2.5v r l = 8 ? + 33h gain = 18db v dd = 5v v dd = 3.6v figure 21. efficiency vs. output power into 8 + 33 h
ssm2305 rev. a | page 9 of 16 0.6 0.5 0.4 0.3 0.2 0.1 0 0 0.5 1.0 1.5 2.0 2.5 3.0 07243-022 power dissipation (w) output power (w) v dd = 5.0v r l = 4 ? + 33h figure 22. power dissipation vs. output power into 4 + 33 h at v dd = 5.0 v 0.20 0.18 0.16 0.14 0.12 0.10 0.08 0.06 0.04 0.02 0 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 07243-023 power dissipation (w) output power (w) v dd = 5.0v r l = 8 ? + 33h figure 23. power dissipation vs. output power into 8 + 33 h at v dd = 5.0 v 0.40 0.35 0.30 0.25 0.20 0.15 0.10 0.05 0 07243-024 power dissipation (w) output power (w) 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 v dd = 3.6v r l = 4 ? + 33h figure 24. power dissipation vs. output power into 4 + 33 h at v dd = 3.6 v 0.14 0.12 0.10 0.08 0.06 0.04 0.02 0 07243-025 power dissipation (w) output power (w) 00 . 2 0.1 0.40.3 0.5 0.6 0.7 0.8 0.9 1.0 v dd = 3.6v r l = 8 ? + 33h figure 25. power dissipation vs. output power into 8 + 33 h at v dd = 3.6 v 800 700 600 500 400 300 200 100 0 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 07243-026 supply current (ma) output power (w) v dd = 5v v dd = 2.5v v dd = 3.6v r l = 4 ? + 33h figure 26. supply current vs. output power into 4 + 33 h 450 400 350 300 250 200 150 100 50 0 00.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 07243-027 supply current (ma) output power (w) v dd = 5v v dd = 2.5v v dd = 3.6v r l = 8 ? + 33h figure 27. supply current vs. output power into 8 + 33 h
ssm2305 rev. a | page 10 of 1 6 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 10 100 pssr (db) 1000 100000 10000 07243-028 frequency (hz) figure 28. power supply reje ction ratio vs. frequency 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 10 100 cmrr (db) 1000 100000 10000 07243-029 frequency (hz) figure 29. common-mode reje ction ratio vs. frequency 8 7 6 5 4 3 2 1 0 ?1 ?2 ?10 0 10 20 sd input output 30 40 50 60 70 80 90 07243-030 voltage (v) time (ms) figure 30. turn-on response 8 7 6 5 4 3 2 1 0 ?1 ?2 ?500 ?400 ?300 ?200 ?100 0 100 200 300 400 500 07243-031 voltage (v) time (s) sd input output figure 31. turn-off response
ssm2305 rev. a | page 11 of 1 6 applications information overview the ssm2305 mono class-d audio amplifier features a filterless modulation scheme that greatly reduces the external components count that, in turn, conserves board space, thereby reducing systems cost. the ssm2305 does not require an output filter, relying instead on the inherent inductance of the speaker coil and the natural filtering of the speaker and human ear to fully recover the audio component of the square wave output. most class-d amplifiers use some variation of pulse-width modulation (pwm), but the ssm2305 uses - modulation to determine the switching pattern of the output devices, resulting in a number of important benefits. - modulators do not produce a sharp peak with many harmonics in the am frequency band, as pulse-width modulators often do. - modulation provides the benefits of reducing the amplitude of spectral components at high frequencies, that is, reducing emi emission that might otherwise be radiated by speakers and long cable traces. due to the inherent spread- spectrum nature of - modulation, the need for oscillator synchronization is eliminated for designs incorporating multiple ssm2305 amplifiers. the ssm2305 also offers protection circuits for overcurrent and temperature protection. 0 7243-032 shutdown 0.1f vdd pop/click suppression out+ out? in+ vbatt 2.5v to 5.5v in? modulator ( - ) gnd 10f 47nf* 47nf* *input capacitors are optional if input dc common-mode voltage is approximately v dd /2. external gain settings = 296k ? /(37k ? + r ext ) sd a udio in? a udio in+ ssm2305 37k? 296k ? 296k ? 37k? r ext r ext fet driver bias internal oscillator figure 32. differential input configuration, user-adjustable gain 07243-033 shutdown 0.1f vdd pop/click suppression out+ out? modulator ( - ) gnd 10f sd ssm2305 37k? 296k ? 296k ? 37k? r ext r ext fet driver bias internal oscillator external gain settings = 296k ? /(37k ? + r ext ) in+ in? a udio in+ v bat t 2.5v to 5.5v 47nf 47nf figure 33. single-ended input conf iguration, user-adjustable gain
ssm2305 rev. a | page 12 of 1 6 gain the ssm2305 has a default gain of 18 db that can be reduced by using a pair of external resistors with a value calculated as follows: external gain settings = 296 k/(37 k + r ext ) pop-and-click suppression voltage transients at the output of audio amplifiers can occur when shutdown activates or deactivates. voltage transients as low as 10 mv can be heard as audio pops in the speaker. clicks and pops can also be classified as undesirable audible transients gener- ated by the amplifier system and, therefore, as not coming from the system input signal. such transients can be generated when the amplifier system changes its operating mode. for example, the following can be sources of audible transients: system power-up/ power-down, mute/unmute, input source change, and sample rate change. the ssm2305 has a pop-and-click suppression architecture that reduces these output transients, resulting in noiseless activation and deactivation. output modulation description the ssm2305 uses three-level, - output modulation. each output is able to swing from gnd to vdd, and vice versa. ideally, when no input signal is present, the output differential voltage is 0 v because there is no need to generate a pulse. in a real-world situation, there are always noise sources present. due to this constant presence of noise, a differential pulse generates when it is required in response to this stimulus. a small amount of current flows into the inductive load when the differential pulse is generated. however, most of the time output differential voltage is 0 v due to the analog devices patented three-level, - output modulation. this feature ensures that the current flowing through the inductive load is small. when the user wants to send an input signal, an output pulse is generated to follow the input voltage. the differential pulse density is increased by raising the input signal level. figure 34 depicts three-level, - output modulation with and without input stimuli. 07243-003 output > 0v +5v 0v out+ +5v 0v out? +5v 0v vout output < 0v +5v 0v out+ +5v 0v out? 0v ?5v vout output = 0v out+ +5v 0v +5v 0v out? +5v ?5v 0v vout figure 34. 3-level, - output modulation with and without input stimuli layout as output power continues to increase, care needs to be taken to lay out pcb traces and wires properly between the amplifier, load, and power supply. a good practice is to use short, wide pcb tracks to decrease voltage drops and minimize inductance. ensure that track widths are at least 200 mil for every inch of track length for lowest dc resistance (dcr), and use 1 oz or 2 oz of copper pcb traces to further reduce ir drops and inductance. a poor layout increases voltage drops, consequently affecting efficiency. use large traces for the power supply inputs and amplifier outputs to minimize losses due to parasitic trace resistance. proper grounding guidelines help improve audio performance, minimize crosstalk between channels, and prevent switching noise from coupling into the audio signal. to maintain high output swing and high peak output power, the pcb traces that connect the output pins to the load and supply pins should be as wide as possible to maintain the minimum trace resistances. it is also recommended that a large ground plane be used for minimum impedances. in addition, good pcb layouts isolate critical analog paths from sources of high interference. separate high frequency circuits (analog and digital) from low frequency circuits. properly designed multilayer pcbs can reduce emi emission and increase immunity to the rf field by a factor of 10 or more compared with double-sided boards. a multilayer board allows a complete layer to be used for the ground plane, whereas the ground plane side of a double-sided board is often disrupted with signal crossover. if the system has separate analog and digital ground and power planes, place the analog ground plane underneath the analog power plane, and, similarly, place the digital ground plane underneath the digital power plane. there should be no overlap between analog and digital ground planes or analog and digital power planes. input capacitor selection the ssm2305 does not require input coupling capacitors if the input signal is biased from 1.0 v to v dd ? 1.0 v. input capacitors are required if the input signal is not biased within this recom- mended input dc common-mode voltage range, if high-pass filtering is needed, or if using a single-ended source. if high-pass filtering is needed at the input, the input capacitor, together with the input resistor of the ssm2305, forms a high-pass filter whose corner frequency is determined by the following equation: f c = 1/(2 r in c in ) the input capacitor can significantly affect the performance of the circuit. not using input capacitors degrades both the output offset of the amplifier and the dc psrr performance.
ssm2305 rev. a | page 13 of 1 6 proper power supply decoupling to ensure high efficiency, low total harmonic distortion (thd), and high psrr, proper power supply decoupling is necessary. noise transients on the power supply lines are short duration voltage spikes. although the actual switching frequency can range from 10 khz to 100 khz, these spikes can contain frequency components that extend into the hundreds of megahertz. the power supply input needs to be decoupled with a good quality low esl, low esr capacitor, usually of around 4.7 f. this capacitor bypasses low frequency noises to the ground plane. for high frequency transient noise, use a 0.1 f capacitor as close as possible to the vdd pin of the device. placing the decoupling capacitor as close as possible to the ssm2305 helps maintain efficient performance.
ssm2305 rev. a | page 14 of 1 6 outline dimensions exposed pad is not connected internal ly. for increased reliabilit y of the solder joints and maximum thermal capability it is recommended that the pad be soldered to the ground plane. 061507-b 1 exposed pa d (bottom view) 0.50 bsc pin 1 indicator 0.50 0.40 0.30 top view 12 max 0.70 max 0.65 typ 0.90 max 0.85 nom 0.05 max 0.01 nom 0.20 ref 1.89 1.74 1.59 4 1.60 1.45 1.30 3.25 3.00 sq 2.75 2.95 2.75 sq 2.55 5 8 pin 1 indicator s eating pl ane 0.30 0.23 0.18 0.60 max 0.60 max figure 35. 8-lead lead frame chip scale package [lfcsp_vd] 3 mm 3 mm body, very thin, dual lead (cp-8-2) dimensions shown in millimeters compliant to jedec standards mo-187-aa 0.80 0.60 0.40 8 0 4 8 1 5 pin 1 0.65 bsc seating plane 0.38 0.22 1.10 max 3.20 3.00 2.80 coplanarity 0.10 0.23 0.08 3.20 3.00 2.80 5.15 4.90 4.65 0.15 0.00 0.95 0.85 0.75 figure 36. 8-lead mini small outline package [msop] (rm-8) dimensions shown in millimeters ordering guide model temperature range package desc ription package option branding ssm2305cpz-r2 1 ?40c to +85c 8-lead lead frame chip scale package [lfcsp_vd] cp-8-2 y10 ssm2305cpz-reel 1 ?40c to +85c 8-lead lead frame chip scale package [lfcsp_vd] cp-8-2 y10 SSM2305CPZ-REEL7 1 ?40c to +85c 8-lead lead frame chip scale package [lfcsp_vd] cp-8-2 y10 ssm2305rmz-r2 1 ?40c to +85c 8-lead mini small outline package [msop] rm-8 y10 ssm2305rmz-reel 1 ?40c to +85c 8-lead mini small outline package [msop] rm-8 y10 ssm2305rmz-reel7 1 ?40c to +85c 8-lead mini small outline package [msop] rm-8 y10 ssm2305-evalz 1 evaluation board wi th lfcsp model 1 z = rohs compliant part.
ssm2305 rev. a | page 15 of 1 6 notes
ssm2305 rev. a | page 16 of 16 notes ?2008 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d07243-0-7/08(a)

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